RAM ERROR DETECTION & CORRECTION USING HVD IMPLEMENTATION

Authors

  • Narinder Pal Singh ECE Department, GTBKIET, Malout, India
  • Sukhjit Singh ECE Department, GTBKIET, Malout, India
  • Vikrant Sharma ECE Department, CTIEMT, Jalandhar, India
  • Amandeep Sehmby ECE Department, CTIEMT, Jalandhar, India

DOI:

https://doi.org/10.19044/esj.2013.v9n33p%25p

Abstract

Data that is either transmitted over communication channel (e.g.
bus) or stored in memory is not completely error free. RAM memory cell contents can change spuriously due to some electromagnetic interference. In magnetic storage devices such as disks, magnetic flux density increases could cause one or more bits to flip (change that value). Exposure to high speed α ray particles is a prominent problem in all the semiconductor memories used for various communication applications. So, in this paper, an error detection and correction method to protect the RAM against the errors is proposed. This method is based on 2-d parities. The parity bits are calculated at the transmitter end for each row, column and diagonal in slash and backslash directions in a memory array. The parities are regenerated at the receiver end. The comparison of transmitted and received parity bits detects the error. As soon as the error is detected, the code corrects the detected error. This method is a promising technique to detect and correct errors in semiconductor memories in presence of large electromagnetic interference with less computational complexity.

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Published

2013-11-30

How to Cite

Pal Singh, N., Singh, S., Sharma, V., & Sehmby, A. (2013). RAM ERROR DETECTION & CORRECTION USING HVD IMPLEMENTATION. European Scientific Journal, ESJ, 9(33). https://doi.org/10.19044/esj.2013.v9n33p%p