3D-NUMERICAL SIMULATION OF NANOSCALE Pi GATE SOI N- MOSFET TRANSISTOR WITH HIGH-k DIELECTRIC AND GRDUAL DOPING OF THE CHANNEL

Abstract

The Pi gate SOI MOSFET is a very good candidate for future VLSI due to its simple architecture and better performance: better control over short channel effects (SCEs) and reduced power dissipation due to reduced gate leakage currents. In this paper, we present the results of a 3D-numerical simulation of nanoscale Pi gate SOI MOSFET transistor. 3D-device structure, based on technology SOI [Silicon-On-Insulator] is described and simulated by using SILVACO TCAD tools. As the oxide thickness scales below 2 nm, leakage currents due to tunneling increase drastically, leading to high power consumption and reduced device reliability. Replacing the silicon dioxide gate dielectric with a high-κ material allows increased gate capacitance without the associated leakage effects. To improve also the performance of the transistor Pi gate SOI MOSFET and to reduce the parasitic effects of to the structure SOI, we introduced the gradual doping of the channel.