DESIGN AND PERFORMANCE VERIFICATION OF CURRENT CONVEYOR BASED PIPELINE A/D CONVERTER USING 180 NM TECHNOLOGY

Abstract

This paper reports a design and performance verification of pipeline Analog to Digital Convertor (ADC) using a second generation current conveyor for increasing accuracy, bandwidth and decrising power desipation of an ADC. The current conveyor used in this design is based on the CMOS inverter which works in transconductance mode rather than traditional current conveyor so that the low voltage operations would also be carried out easily, which makes the ADC more versatile. Extensive simulations along with performance evaluation of ADC are done to check the operating frequency range and band width. Results are reported that shows the capability and effectiveness of the proposed design. Authors have verified the capability of this design to operate over the high frequency range (1 Hz to 100GHz). Best simulation results obtained on cadence environment with 180nm technology. Also the layout design is carried out in the cadence virtuoso environment and verified the performance of the proposed design. Finally results of complete ADC design is reported.