GALUPA, Nicolae. Logic Circuits Timing Analysis Using Timed Logic Variables. European Scientific Journal, ESJ, [S. l.], v. 12, n. 18, p. 35, 2016. DOI: 10.19044/esj.2016.v12n18p35. Disponível em: https://test.eujournal.org/index.php/esj/article/view/7598. Acesso em: 19 apr. 2025.